The timetable can be found here.

Technical and social activities

The program includes:

  • Eight technical sessions, with 26 talks (see details below).
  • A welcome reception and cocktail at the Museo Patio Herreriano (Contemporary Art Museum) on Wednesday, 6th July.
  • A talk delivered by Prof. Uday Bondhugula on optimization infrastructures for compiler construction (see details below).
  • A guided tour to the National Sculpture Museum on Thursday, 7th.
  • A Gala Dinner at the Parrilla de San Lorenzo, one of the best restaurants in the city, on Thursday 7th.
  • A “Tapas Lunch” on Friday, 8th at the bars located around the city center.

Session A: Heterogeneous Computing (Wednesday 6, 9:15 to 10:30)

Session B: Intermediate Representation (Wednesday 6, 11:00 to 12:30)

Session C: Speculation and Transactional Memory (Wednesday 6, 13:30 to 14:45)

Session D: Memory Hierarchies and Programming Tools (Wednesday 6, 15:15 to 16:45)

Invited Lecture: Dr. Uday Bondhugula (Thursday 7, 9:00 to 10:30)

Title: Reusable Infrastructure for Optimization in Domain-Specific and General-Purpose Compilers

Abstract: Challenges in compiler parallelization and optimization for the multicore era can broadly be classified into two categories: one that makes progress on optimization support in general-purpose compilers for high-performance languages (eg. LLVM, GCC, other commercial production compilers, and research compilers), and the other in building domain-specific compilers/code generators with an objective to provide effective automatic parallelization, optimization, and programmer productivity. This talk will motivate the need to build optimization infrastructure that benefits and can be shared by both approaches, and discuss possible ways to accomplish this. Two particular example domains will be presented as case studies: (1) image processing pipelines, and (2) numerical solvers for partial differential equations. Short video demos will also be performed.

Uday Bondhugula is an Assistant Professor in the Department of Computer Science and Automation at the Indian Institute of Science (IISc) in Bangalore, India. His research interests are in programming and compiler/runtime technologies for multicore architectures with an emphasis on high performance and automatic parallelization, the design of domain-specific compilers, and the polyhedral compiler framework. Before joining IISc, he was with the Advanced Compiler Technologies group at the IBM T.J. Watson Research Center, Yorktown Heights, New York. He received his Ph.D. in Computer Science and Engineering from the Ohio State University, and his B-Tech in Computer Science and Engineering from the Indian Institute of Technology, Madras. Web:

Session E: Accelerators and IR (Thursday 7, 11:00 to 12:30)

Session F: Balance and energy consumption (Thursday 7, 13:30 to 14:45)

 Session G: Code Analysis (Friday 8, 9:00 to 10:30)

Session H: Domain Specific Languages (Friday 8, 11:00 to 12:15)



Compilers for Parallel Computing